| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device in which disturbance voltage for a non-selection memory cell at the time of write is relaxed. <P>SOLUTION: The nonvolatile semiconductor storage device comprises a plurality of memory cells 60 arranged in a matrix state, a memory cell array 40 having a plurality of word lines 10, a plurality of bit lines 20, and a plurality of source lines 30, a word line control circuit 100 controlling the plurality of word lines 10, and a line control circuit 200 controlling a plurality of bit lines 20 and the plurality of source lines 30. Further, in the nonvolatile semiconductor storage device, the memory cell 60 has a gate electrode 62 connected to the word line 10, a first impurity region fd, a second impurity region sd, and a trap region of electrons formed between the gate electrode 62 and a substrate 63 and at least at the first impurity region fd side out of the first impurity region fd side and the second impurity region sd side, the word line control circuit 100 supplies selection voltage to a selection word line connected to the selection memory cell when write operation is performed to the selection memory cell, and supplies accidental deletion preventing voltage to a non-selection word line. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
