| 摘要 |
PROBLEM TO BE SOLVED: To provide a D/A conversion device in which influence of jitter is avoided and noise at the time of silence is removed. SOLUTION: SinceΔΣmodulation output processed in accordance with a multiplication clock of 1024fs, which a PLL part 60 generates, is formed in synchronizing with a clock CK of 256fs, influence of jitter (time-base error) existing in the multiplication clock is avoided. Since a bias addition part 30 supplies bias of a minute level so that a value remaining in the first integrator 21a of aΔΣmodulator 20 is suppressed to a value within a prescribed range, noise at the time of silence in high-orderΔΣmodulation is removed. COPYRIGHT: (C)2005,JPO&NCIPI
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