POWER SAVING OPERATION OF AN APPARATUS WITH A CACHE MEMORY
摘要
An apparatus that contains an instruction processing circuit (14), a main memory (18) addressable by the instruction processing circuit (14) and a cache memory (16). In a normal mode the cache memory (16) is used to cache a part of data and/or instructions that the instruction processing circuit (14) addresses in the main memory (18) during execution, and to substitute cached data and/or instructions when the instruction processing circuit (14) addresses the data and/or instructions in the main memory (18). The circuit is able to switch to a low power operating mode. Upon the switch an interrupt program for executing a function during operation in the low power operating mode is loaded into the cache memory (16) from the main memory (18). Power supply to the main memory (18) is then switched off, but keeping at least a part of the cache memory (16) continuous to receive power supply. This part ensures that the program of instructions for executing the function is available to the instruction processing circuit. The program is executed from said at least part of the cache memory (16) in the low power operating mode.
申请公布号
WO2005026928(A2)
申请公布日期
2005.03.24
申请号
WO2004IB51602
申请日期
2004.08.30
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.;VAN DER HEIJDEN, GERARDUS, W., T.