| 摘要 |
PROBLEM TO BE SOLVED: To provide a pipeline processing system which operates at high speed and realizes reduction of power consumption, and also to provide an information processor applied therewith. SOLUTION: In the case of a decoding process, a decoder/encoder circuit 115 accesses a first memory and a second memory in a parallel state according to state information ST0 or ST1 to preform the decoding process, stores data after the decoding process into a tracking memory, and transfers the data stored in the tracking memory to a host device 117 according to a request from the host device 117. In an encoding process, the decoder/encoder circuit 115 writes user data transferred from the host device 117 in block units into a third memory as a tracking buffer to start the encoding process, accesses the plurality of memories in a parallel state according to the state information ST0 or ST1 to perform the encoding process, and performs output to a clock generation circuit 113. COPYRIGHT: (C)2005,JPO&NCIPI
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