发明名称 |
Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method |
摘要 |
A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part of a channel region provided in the peripheral wall of the column-shaped semiconductor layer in opposed relation to the gate electrode of the selection transistor.
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申请公布号 |
US2005063237(A1) |
申请公布日期 |
2005.03.24 |
申请号 |
US20040941505 |
申请日期 |
2004.09.14 |
申请人 |
FUJIO MASUOKA;SHARP KABUSHIKI KAISHA |
发明人 |
MASUOKA FUJIO;SAKURABA HIROSHI;MATSUOKA FUMIYOSHI;UENO SYOUNOSUKE;MATSUYAMA RYUSUKE;HORII SHINJI;TANIGAMI TAKUJI |
分类号 |
G11C16/02;G11C7/00;G11C16/04;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C7/00 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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