发明名称 |
Dual mask capacitor for integrated circuits |
摘要 |
An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.
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申请公布号 |
US2005063138(A1) |
申请公布日期 |
2005.03.24 |
申请号 |
US20040831471 |
申请日期 |
2004.04.23 |
申请人 |
ROST TIMOTHY A.;BURKE EDMUND;PAPA RAO SATYAVOLU S.;KEAGY ROSE ALYSSA |
发明人 |
ROST TIMOTHY A.;BURKE EDMUND;PAPA RAO SATYAVOLU S.;KEAGY ROSE ALYSSA |
分类号 |
H01L21/02;H01L21/768;(IPC1-7):H01G4/228 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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