发明名称 Output stage, amplifier and associated method for limiting an amplifier output
摘要 A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.
申请公布号 US6870426(B2) 申请公布日期 2005.03.22
申请号 US20030609209 申请日期 2003.06.27
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 DASHTESTANI AHMAD;HALBERT JOEL MARTIN;VARNER ALAN LEE
分类号 H03F3/26;H03F3/45;(IPC1-7):H03F3/26 主分类号 H03F3/26
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