Method and device for characterizing a CMOS logic cell to be produced in a technology of the partially depleted silicon-on-insulator type

摘要

A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.