发明名称 Prefetch control in a data processing system
摘要 A data processing system (10) includes an interconnect (22) where a first interconnect master (12) and a second interconnect master (14) are coupled to the interconnect. A shared storage (35) is coupled to the interconnect for use by the first and second interconnect masters. The data processing system also includes a first control storage circuit (60, 64) which corresponds to the first interconnect master and a second control storage circuit (62, 66) which corresponds to the second interconnect master. In one embodiment, prefetch circuitry (40) is coupled to the first control storage circuit and to the second control storage circuit for selecting one of the first and second control storage circuits based upon which one of the first and second interconnect masters is requesting an access to the shared storage. The prefetch circuitry can then use the selected control storage circuit to determine a prefetch operation triggered by the access to the shared storage.
申请公布号 US6871246(B2) 申请公布日期 2005.03.22
申请号 US20030431285 申请日期 2003.05.07
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 MOYER WILLIAM C.
分类号 G06F12/08;G06F13/12;G06F13/16;G06F13/28;G06F13/38;G06F13/42;(IPC1-7):G06F13/38 主分类号 G06F12/08
代理机构 代理人
主权项
地址