发明名称 Phase locked loop circuit with self adjusted tuning hiep the pham
摘要 A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, one or more second inputs to receive one or more tuning range control signals, and an output to provide an oscillation output signal, a phase detector having inputs to receive the oscillation output signal and a reference signal, a charge pump having an input coupled to the output of the phase detector and having an output to generate the control voltage, a loop filter having an input to receive the control voltage and having a control terminal, and a controller having inputs to receive the control voltage, a high reference voltage, a low reference voltage, and one or more mode signals, and having a first output connected to the control terminal of the loop filter and second outputs to generate the tuning range signals.
申请公布号 US2005057289(A1) 申请公布日期 2005.03.17
申请号 US20030662554 申请日期 2003.09.15
申请人 PHAM HIEP THE 发明人 PHAM HIEP THE
分类号 H03L7/089;H03L7/099;H03L7/10;(IPC1-7):H03L7/06 主分类号 H03L7/089
代理机构 代理人
主权项
地址