DATA SIGNAL RECEPTION LATCH CONTROL USING CLOCK ALIGNED TO STROBE SIGNAL

摘要

PROBLEM TO BE SOLVED: To eliminate a limitation on the clock frequency caused by the strobe signal delay variation due to voltage and/or temperature (PVT) variations so that data signals is driven with sufficiently high reliability and latched in appropriate timing by a memory controller. SOLUTION: A clock signal aligned to an edge of a strobe signal received from a transmitter is generated. One or more data signals received from the transmitter are latched using the clock signal. COPYRIGHT: (C)2005,JPO&NCIPI