发明名称 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power
摘要 A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
申请公布号 US2005057556(A1) 申请公布日期 2005.03.17
申请号 US20040949990 申请日期 2004.09.23
申请人 KUBOTA YASUSHI;WASHIO HAJIME;SHIRAKI ICHIRO;MAEDA KAZUHIRO;KAISE YASUYOSHI 发明人 KUBOTA YASUSHI;WASHIO HAJIME;SHIRAKI ICHIRO;MAEDA KAZUHIRO;KAISE YASUYOSHI
分类号 G09G5/00;(IPC1-7):G09G5/00 主分类号 G09G5/00
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