发明名称 |
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
摘要 |
In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
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申请公布号 |
US6867433(B2) |
申请公布日期 |
2005.03.15 |
申请号 |
US20030426566 |
申请日期 |
2003.04.30 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
YEO YEE-CHIA;CHEN HOW-YU;HUANG CHIEN-CHAO;LEE WEN-CHIN;YANG FU-LIANG;HU CHENMING |
分类号 |
H01L21/336;H01L21/84;H01L27/12;H01L29/786;(IPC1-7):H01L29/786 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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