发明名称 METHOD OF FORMING INTERCONNECTION LINES IN A SEMICONDUCTOR DEVICE
摘要 A method of forming a metal line of a semiconductor device is provided to restrain electrical failure of a metal line or a metal plug by using an alloy line. An insulating layer(302) with a damascene pattern composed of a first trench(304a) and a via hole(306) and a second trench(304b) is formed on a lower layer(300). A diffusion barrier(308), a first seed layer, and a first conductive layer are sequentially formed thereon. At this time, the via hole and the second trench are completely filled with the first conductive layer. An additional material layer and a second conductive layer are sequentially formed on the resultant structure to fill completely the first trench. The insulating layer is exposed to the outside by planarizing the resultant structure. An alloy layer(314) is formed in the via hole and the first trench by using a heat treatment.
申请公布号 KR20050026272(A) 申请公布日期 2005.03.15
申请号 KR20030063293 申请日期 2003.09.09
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 AHN, JEONG HOON;HAH, SANG ROK;HONG, DUK HO;JEONG, SE YOUNG;LEE, HYO JONG;LEE, JONG WON;LEE, KYOUNG WOO;LEE, SOO GEUN;SON, HONG SEONG;SUH, BONG SEOK
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
代理机构 代理人
主权项
地址
您可能感兴趣的专利