| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a memory in which a packaging area is reduced and whose yield is improved by reducing the number of elements and the load on peripheral circuits is reduced, and the driving method of the memory. <P>SOLUTION: The memory comprises memory cells each of which includes a storage element in an area on which a bit line and a word line intersect with each other across an insulator, a column decoder, and a selector including a clocked inverter. The input node of the clocked inverter is connected to the bit line, an output node is connected to a data line, the gate of a P-type transistor whose source or drain is connected to a high potential power supply VDD and the gate of an N type transistor whose source or drain is connected to a low potential power supply VSS out of a plurality of transistors connected in series to constitute the clocked inverter are connected to the column decoder. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
