发明名称 Advanced processor translation lookaside buffer management in a multithreaded system
摘要 An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
申请公布号 US2005055510(A1) 申请公布日期 2005.03.10
申请号 US20040898150 申请日期 2004.07.23
申请人 HASS DAVID T.;MUKHERJEE BASAB 发明人 HASS DAVID T.;MUKHERJEE BASAB
分类号 G06F12/08;H04L12/56;(IPC1-7):G06F12/00 主分类号 G06F12/08
代理机构 代理人
主权项
地址