Delay regulation circuit for clock-controlled integrated circuit, e.g. semiconductor memory, has input clock signal frequency reduced before subjecting it to variable delay and restoring original clock signal frequency

摘要

The delay regulation circuit (1) has a delay device (2) with a controlled delay time connected in series between an input terminal (5) for the clock signal to be delayed and an output terminal (6) for the delayed clock signal. The delay device has 3 successive stages (2-A,2-B,2-C), its first stage reducing the frequency of the received clock signal, its second stage supplied with a control signal (vn,vp) by a control device (4), dependent on the phase difference between the clock signal to be delayed and the delayed clock signal and its third stage restoring the original clock signal frequency.