| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce increases of a chip area and a cost in a pixel interpolation operation caused by possessing a large capacity memory for a bidirectional interpolation operation, a large capacity memory for storing final computation results after the final interpolation, and an address generator for controlling read/write of memory data respectively inside a circuit. <P>SOLUTION: An output control unit 30 consisting of a counter 23, a decoder 25 and a shift register 28 is provided. The empty region of a final interpolation result storage memory 20 for storing the final computation results of the pixel interpolation operation is used also as a vertical interpolation calculation result storage memory. In addition, a method of writing data into the memory 20 is devised so that forward prediction data 35 stored in the memory 20 is read with the timing aligned with the output of backward prediction data from a horizontal/vertical interpolation computing unit 13. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
