发明名称 SELECTIVE ETCH PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC OF HIGH DIELECTRIC VALUE TO PREVENT GATE ELECTRODE FROM BEING CONSIDERABLY LIFTED OR UNDERCUT WHILE SUBSTRATE UNDER DIELECTRIC LAYER IS NOT MEANINGFULLY DAMAGED
摘要 PURPOSE: A selective etch process for fabricating a semiconductor device with a gate dielectric of a high k value is provided to prevent a gate electrode from being considerably lifted or undercut while a substrate under a dielectric layer is not meaningfully damaged by selectively eliminating the first part of a gate dielectric layer with a high k value with respect to the second part of the gate dielectric layer of the high k value. CONSTITUTION: A gate dielectric layer(101) of a high k value is formed on a substrate. The first part(103) of the gate dielectric layer of the high k value is varied to guarantee that the first part of the gate dielectric layer with the high k value is selectively removed with respect to the second part(104) of the gate dielectric layer of the high k value.
申请公布号 KR20050021943(A) 申请公布日期 2005.03.07
申请号 KR20040068106 申请日期 2004.08.27
申请人 INTEL CORP. 发明人 BRASK JUSTIN K.;CHAU ROBERT S.;DOCZY MARK L.;KAVALIEROS JACK;METZ MATTHEW V.;SHAH UDAY;TURKOT ROBERT B. JR.
分类号 H01L21/311;(IPC1-7):H01L21/336 主分类号 H01L21/311
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