Cache memory with asynchronous readout and data memory access control device with such a cache memory

摘要

The memory has a management circuit (CMC) provided with an asynchronous circuit (AAR) that reads from a cache memory and with a hard-wired logic. The management circuit receives, at input, a reference label for simultaneously comparing all the labels present in the memory. The management circuit selects the data base associated to the label that is similar to the reference label and supplies it as output for the reading circuit. Independent claims are also included for the following: (a) an access control device for data memory (b) a control access method for data memory.