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发明名称
半导体积体电路
摘要
本发明提供一种输出电路,其输出MOS电晶体的源极部之寄生电容、寄生电阻小,而且经强化可高速进行电路动作的ESD耐受能力。其解决的方式系在输出端子与接地端子之间(或电源端子之间)设置专用之静电保护电路;此静电保护电路系在源极与汲极的所有范围,都是由矽化的第1MOS电晶体与第2MOS电晶体的串级连接所构成的。两电晶体的闸极电极皆连接到内部电路,第1MOS电晶体的源极扩散层与第2MOS电晶体的汲极扩散层,系分别隔离形成,并以金属配线连接。
申请公布号
TW200509372
申请公布日期
2005.03.01
申请号
TW093121912
申请日期
2004.07.22
申请人
NEC电子股份有限公司
发明人
森下泰之
分类号
H01L27/088;H03K19/0175
主分类号
H01L27/088
代理机构
代理人
周良谋;周良吉
主权项
地址
日本
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