发明名称 HIGH-SPEED MODULE FOR ADDING/COMPARING/SELECTING FOR USE WITH WITTERBY DECODER
摘要 FIELD: Witterby algorithm applications. ^ SUBSTANCE: system has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. ^ EFFECT: higher efficiency. ^ 2 cl, 9 dwg
申请公布号 RU2246751(C2) 申请公布日期 2005.02.20
申请号 RU20020113295 申请日期 2000.10.23
申请人 发明人 KHANSKVIN DEHVID
分类号 G06F11/10;G06F7/38;H03M13/41 主分类号 G06F11/10
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