发明名称 Programmable phase-locked loop fractional-N frequency synthesizer
摘要 A fractional-N PLL with programmable fractionality having a phase detector and an oscillator is disclosed. The phase detector is for receiving a reference signal having a reference frequency and the oscillator is for providing an output signal having an output frequency. The fractional-N PLL comprises a divider for performing frequency divisions by applying selectable divisors, the divider being disposed in the loop of the fractional-N PLL for receiving the output signal from the oscillator and in response thereto provide a first signal having an averaged frequency. The fractional-N PLL also comprises a first counter connected to the divider in the loop of the fractional-N PLL for receiving the first signal, the first counter for performing a first plurality of counts to a predetermined first integer in response to the averaged frequency of the first signal, wherein the first counter provides a second signal having a loop frequency in accordance with the first plurality of counts to the phase detector for providing the detection of the phase difference between the reference signal and the second signal.
申请公布号 US2005036580(A1) 申请公布日期 2005.02.17
申请号 US20030638336 申请日期 2003.08.12
申请人 RANA RAM SINGH 发明人 RANA RAM SINGH
分类号 H03D3/24;H03L7/197;(IPC1-7):H03D3/24 主分类号 H03D3/24
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