| 摘要 |
A memory comprising a memory array, a plurality of word lines, a plurality of bit lines, a word line decoder, an equalizer and an equalization control apparatus is provided to meet the requirement of the completion of bit line equalization prior to the turn on of word lines. The memory array is arranged in columns and rows. The word lines are connected to the rows of the memory array. The bit lines connected to the columns of the memory array. The word line decoder is connected to the word lines for selecting one of the word lines. The equalizer is connected to the bit lines for equalizing the bit lines to a desired voltage. The equalization control apparatus serves for monitoring the equalizer to disable the word line decoder when the equalizer performs a equalization operation and enable the word line decoder when the equalization operation is completed.
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