发明名称 Integrated circuit package and manufacturing method therefor with unique interconnector
摘要 An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
申请公布号 US6855573(B2) 申请公布日期 2005.02.15
申请号 US20020251231 申请日期 2002.09.19
申请人 ST ASSEMBLY TEST SERVICES LTD. 发明人 LI JIAN JUN;SHIM IL KWON;BADAKERE GURUPRASAD
分类号 H01L21/60;H01L23/31;H01L23/498;H01L23/50;(IPC1-7):H01L21/44;H01L23/12;H05K7/08 主分类号 H01L21/60
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