| 摘要 |
A large level three (L3) cache is integrated within the system chipset. The L3 cache is comprised of multiple embedded memory cache arrays. Each array is accessible independently of each other, providing parallel access to the L3 cache. By placing the L3 cache within the chipset, it is closer to the system processor with respect to the system memory. By using independent arrays, the L3 cache can handle numerous simultaneous requests. This reduces average memory latency and thus, increases system bandwidth and overall performance. By using embedded memory, the L3 cache can be implemented on the chipset and be much larger than the L1 and L2 caches without substantially increasing the size of the chipset and system.
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