| 摘要 |
While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation region, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film comprising the silicon oxide film only.
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