发明名称 |
Hiding error detecting/correcting latency in dynamic random access memory (DRAM) |
摘要 |
System and method for hiding error detecting and correcting latency in a dynamic random access memory refresh cycle. A preferred embodiment comprises in a first memory refresh cycle, detecting the presence of an error in information retrieved from a memory element and in a second memory refresh cycle, writing corrected information back to the memory element containing the erroneous information, wherein the second memory refresh cycle is a memory refresh cycle immediately following the first memory refresh cycle.
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申请公布号 |
US6853602(B2) |
申请公布日期 |
2005.02.08 |
申请号 |
US20030434624 |
申请日期 |
2003.05.09 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HUANG CHIEN-HUA |
分类号 |
G11C7/10;G11C11/406;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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