发明名称 ARRAY CONTROL UNIT
摘要 PROBLEM TO BE SOLVED: To eliminate the trouble that there is the need of preventing the performance of a processor from being degraded owing to occurrence of an interruption. SOLUTION: In the event that an interruption occurs in a PCI device connected to a PCI bus divided by a PCI-PCI bridge, a content of an internal register of the device is mirrored to a storage area of the PCI-PCI bridge. Access is made to the mirrored content for read-accessing the internal register of the PCI device where the interruption occurred from the processor. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005031933(A) 申请公布日期 2005.02.03
申请号 JP20030195523 申请日期 2003.07.11
申请人 HITACHI LTD 发明人 NAKAMURA TOSHIKATSU
分类号 G06F13/24;G06F13/36;(IPC1-7):G06F13/24 主分类号 G06F13/24
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