| 摘要 |
PURPOSE: A delay locked loop for generating multi-phase clocks without a voltage-controlled oscillator is provided to output the multi-phase clocks stably by preventing the multi-phase clock to be synchronized with harmonics of an input clock signal frequency. CONSTITUTION: A delay locked loop for generating multi-phase clocks includes a clock delay member, a phase detector, a charge pump(40), and a voltage-current converter(6). The clock delay member includes a plurality of delay members which sequentially delay an input clock signal to output the multi-phase clock signals. The phase detector detects a phase difference between the input clock signal and the output clock signals of the clock delay member to adjust a delay amount of the clock delay member. The delay locked loop further includes a clock position detector(20) which detects a delay position of the clock signal outputted from the clock delay member and outputs another control signal to adjust the delay amount of the clock delay member.
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