| 摘要 |
Semiconductor memory devices are provided which include an array of memory cells, an array of reference cells, and a plurality of sense amplifiers that are associated with respective of the memory cells. The reference cells have a first capacitor that is coupled to a first supply voltage, to a first complementary bit line associated with one of the memory cells and to a second complementary bit line that is associated with a different memory cell. The sense amplifiers are configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line. These semiconductor memory devices may output bit cell data without a separate reference voltage generator.
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