发明名称 |
Method, system, and apparatus for an efficient power dissipation |
摘要 |
A processor that includes a digital throttle to monitor the activity of the execution pipeline and to change a frequency of a first or second PLL clock within a single clock cycle based on a power state.
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申请公布号 |
US2005022037(A1) |
申请公布日期 |
2005.01.27 |
申请号 |
US20030624366 |
申请日期 |
2003.07.21 |
申请人 |
BURNS JAMES S.;BODAS DEVADATTA V.;RUSU STEFAN I.;MUTHYALAPATI SUDHIR |
发明人 |
BURNS JAMES S.;BODAS DEVADATTA V.;RUSU STEFAN I.;MUTHYALAPATI SUDHIR |
分类号 |
G06F1/08;G06F1/32;(IPC1-7):G06F1/26 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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