发明名称 STRUCTURE OF HIGH VOLTAGE TRANSISTOR WITH SHALLOW TRENCH ISOLATION LAYER TO PREVENT TURN-ON FAIL CAUSED BY HUMP CHARACTERISTIC
摘要 PURPOSE: A structure of high voltage transistor with shallow trench isolation layer to prevent a turn-on fail caused by a hump characteristic by forming a drift region surrounding a source/drain region while the drift region is separated from the edge of a shallow trench isolation layer by a predetermined interval. CONSTITUTION: A shallow trench isolation layer(104) is formed on a semiconductor substrate(100) to define an active region and an inactive region. A gate electrode(108) is formed on the substrate by interposing a gate insulation layer(106). A well with implanted impurities of the first conductivity type is formed in the active region of the substrate. A source/drain region with implanted impurities of the second conductivity type is formed in the well at both sides of the gate electrode. A drift region(102) with implanted impurities of the second conductivity type is formed in the well at both sides of the gate electrode to surround the source/drain region, separated from the shallow trench isolation layer by a predetermined interval.
申请公布号 KR20050009797(A) 申请公布日期 2005.01.26
申请号 KR20030048868 申请日期 2003.07.16
申请人 MAGNACHIP SEMICONDUCTOR, LTD. 发明人 YUN, SEOK MAN
分类号 H01L21/76;(IPC1-7):H01L21/76 主分类号 H01L21/76
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