Integrated circuit memory device, has column select IO blocks and N-type sense amplifier blocks arranged in zig-zag layout pattern that spans two rows of zeroth sense amplifier region

摘要

The device has two memory blocks electrically coupled by respective pairs of bit lines. Column select IO blocks (150) and N-type sense amplifier blocks (140) are arranged in a zig-zag layout pattern that spans two rows of a zeroth sense amplifier region. The zig-zag layout sequence of sense amplifier blocks is interleaved with the zig-zag layout sequence of the column select IO blocks.