发明名称 |
PROCESS FOR PLANARIZING ARRAY TOP OXIDE IN VERTICAL MOSFET DRAM ARRAYS |
摘要 |
The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.
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申请公布号 |
US2005014331(A1) |
申请公布日期 |
2005.01.20 |
申请号 |
US20030604361 |
申请日期 |
2003.07.14 |
申请人 |
YANG SHENG-WEI;HUANG CHENG-CHIH;LIAO CHIEN-MAO |
发明人 |
YANG SHENG-WEI;HUANG CHENG-CHIH;LIAO CHIEN-MAO |
分类号 |
H01L21/3105;H01L21/311;H01L21/316;H01L21/8242;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/3105 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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