发明名称 |
SELF-ALIGNING DATA PATH CONVERTER FOR MULTIPLE CLOCK SYSTEMS |
摘要 |
A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26). The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input,signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data. |
申请公布号 |
WO2005006551(A2) |
申请公布日期 |
2005.01.20 |
申请号 |
WO2004US20881 |
申请日期 |
2004.06.30 |
申请人 |
RAYTHEON COMPANY |
发明人 |
CHEUNG, FRANK, N.;CHIN, RICHARD |
分类号 |
G06F1/12;H03K5/135;H04L7/00;H04L7/02 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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