发明名称 |
Digital architecture for reconfigurable computing in digital signal processing |
摘要 |
A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.
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申请公布号 |
US2005015573(A1) |
申请公布日期 |
2005.01.20 |
申请号 |
US20040770122 |
申请日期 |
2004.02.02 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
CAMPI FABIO;TOMA MARIO;LODI ANDREA;CAPPELLI ANDREA;CANEGALLO ROBERTO;GUERRIERI ROBERTO |
分类号 |
G06F9/38;G06F15/78;(IPC1-7):G06F15/00 |
主分类号 |
G06F9/38 |
代理机构 |
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地址 |
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