发明名称 METHOD OF FORMING A LOW-K DUAL DAMASCENE INTERCONNECT STRUCTURE
摘要 A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
申请公布号 WO2004061916(B1) 申请公布日期 2005.01.13
申请号 WO2003US41145 申请日期 2003.12.23
申请人 APPLIED MATERIALS, INC. 发明人 DELGADINO, GERARDO, A.;YE, YAN;SHIN, NEUNGHO;KIM, YUNSANG;XIA, LI-QUN;HUANG, TZU-FANG;LI, LIHUA;CHIU, JOEY;ZHAO, XIAOYE;TIAN, FANG;ZHU, WEN;YIEH, ELLIE
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
代理机构 代理人
主权项
地址