发明名称 IDDQ test methodology based on the sensitivity of fault current to power supply variations
摘要 A method for testing integrated circuits is provided. The method includes providing an excitation voltage to a device, such as a MOSFET. A power supply voltage is also provided to the device, such as a drain to source voltage or VCC. The quiescent power supply current of the device is then measured, such as the IDDQ of the MOSFET. The power supply voltage to the device is then varied, and it is determined whether a change in the IDDQ of the device exceeds a predetermined allowable change.
申请公布号 US6842032(B2) 申请公布日期 2005.01.11
申请号 US20030684119 申请日期 2003.10.10
申请人 LSI LOGIC CORPORATION 发明人 PALUSA CHAITANYA
分类号 G01R31/30;(IPC1-7):G01R31/26 主分类号 G01R31/30
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