METHOD OF FORMING POLYSILICON PLUG OF SEMICONDUCTOR DEVICE USING FIRST AND SECOND INTERLAYER DIELECTRICS WITH DIFFERENT POLISHING RATE FOR PREVENTING WORD LINE FROM BEING EXPOSED TO OUTSIDE

摘要

PURPOSE: A method of forming a polysilicon plug of a semiconductor device is provided to prevent a word line from being exposed to the outside within a peripheral region by using a first and second interlayer dielectric with a different polishing rate. CONSTITUTION: A plurality of stack type patterns composed of a word line(32) and a hard mask layer(34) are formed on a semiconductor substrate(30) with a cell and peripheral region. A spacer(36) is formed at both sidewalls of each stack type pattern. A first interlayer dielectric(38) is formed thereon and planarized. A second interlayer dielectric(40) with a lower polishing rate than that of the first interlayer dielectric is formed thereon. A polysilicon plug contact hole for exposing the stack type patterns of the cell region is formed in the resultant structure by etching selectively the second and first interlayer dielectrics. A polysilicon layer is deposited thereon. An etch-back process is performed on the polysilicon layer until the second interlayer dielectric of the peripheral region is exposed. CMP(Chemical Mechanical Polishing) is performed on the resultant structure to form polysilicon plugs.