| 摘要 |
There is provided a timing generator capable of absorbing a delay time error of a variable delay circuit without increasing the number of bits of path data and suppressing deterioration of the timing accuracy from the designed value to the minimum. The timing generator is configured to include a selection unit 13 which assigns five-bit delay device candidates to a three-bit partial bit signal of all the bit signals constituting the path data outputted from a linearization memory 12 and selects three delay devices whose number is equal to the bit count of the partial bit signal.
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