An integrated circuit has a high voltage area, a logie area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.
申请公布号
WO2005001937(A2)
申请公布日期
2005.01.06
申请号
WO2004EP51254
申请日期
2004.06.25
申请人
INFINEON TECHNOLOGIES AG;KAKOSCHKE, RONALD;TEMPEL, GEORG;SHUM, DANNY