| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock and data recovery circuit which reduces the circuit scale, the chip size and the power consumption and follows up frequency-modulated input data. <P>SOLUTION: The circuit comprises a phase detector 101 for detecting the phase lag and advance to output UP1/DOWN1 signals upon input of data signals and synchronizing clock signals, integrators 102, 103 for integrating the UP1/DOWN1 signals to output UP2/DOWN2 signals and UP3/DOWN3 signals, respectively, a pattern generator 104 for outputting UP4/DOWN4 signals upon input of the UP3/DOWN3 signals from the integrator 103, a mixer 105 for generating and outputting UP5/DOWN5 signals upon input of the UP2/DOWN2 signals from the integrator 102 and the UP4/DOWN4 signals from the pattern generator, and a phase interpolator 106 for interpolating the phase of an inputted clock signal to output a clock signal, based on the UP5/DOWN5 signal from the mixer. The clock signal outputted from the interpolator is then fed back as a clock to the input of the phase detector. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
