| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the power consumption of a shift register by simplifying the structure of the shift register. <P>SOLUTION: After a plurality of latch circuits are cascaded and an input signal having at least double cycles of that of a clock pulse is made to be shifted by an amount equivalent to one latch according to the clock pulse, a signal in which the output of the n-th latch circuit (n=1, 2, 3, ...) and the output of the (n-1)th latch circuit are ANDed (AND-operated) is made to be a shifting signal of each stage. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
