A modifiable circuit, methods of use and making thereof

摘要

A modifiable circuit for modifying a revision identifier (ID) or default register value, and for coupling at least two adjacent logic blocks in an integrated circuit chip, and methods for manufacturing the same. The circuit comprises a memory cell, a register and a control circuit. The memory cell, which may be termed a "Meta-Memory Cell" (MMCEL), has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The memory cell also has a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks. The interconnect is formed between the at least two adjacent logic blocks by at least one of the first and second metal interconnect structures, wherein a state of the interconnect is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register. The control circuit receives a chip reset signal and the memory cell output to thereby force the data output of the register to a default register value that equals the output of the memory cell, regardless of the data input of the register.