发明名称 SYNCHRONIZING CLOCK ENABLEMENT IN AN ELECTRONIC DEVICE
摘要 A method of synchronizing enablement of a common clock for a main and a second processor in an electronic device having a low-power mode includes a first step of completing a communication activity by the main processor. A next step includes monitoring a clock enable signal from the second processor. A next step includes comparing the timing of the second processor with the known timing of the main processor if the second processor does not have the clock enabled in the monitoring step. A next step includes calculating the the timing needed to synchronize the clock enablement by the second processor to that of the main processor. A next step includes powering up and powering down the second processor under control by the main processor to synchronize the periodic timing of the second processor to that of the main processor.
申请公布号 KR20040111608(A) 申请公布日期 2004.12.31
申请号 KR20047018323 申请日期 2003.04.29
申请人 发明人
分类号 G06F1/04;G06F1/12;G04F8/00;G06F1/32;H04B7/26;H04M1/73 主分类号 G06F1/04
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