发明名称 |
Timer lockout circuit for synchronous applications |
摘要 |
A SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.
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申请公布号 |
US2004264289(A1) |
申请公布日期 |
2004.12.30 |
申请号 |
US20030604168 |
申请日期 |
2003.06.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
JACUNSKI MARK D;NORRIS ALAN D;WEINSTEIN SAMUEL K |
分类号 |
G11C7/10;G11C8/00;G11C11/4076;G11C11/408;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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