发明名称 Semiconductor memory testing method and apparatus
摘要 A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count FN is equal to or greater than a given number TF, a plurality of erasure operations are conducted consecutively next. If FN<TF, a single erasure operation is conducted next, subsequently followed by a read-out test. The erasure operations and the read-out tests are repeated.
申请公布号 US6836863(B2) 申请公布日期 2004.12.28
申请号 US20010925138 申请日期 2001.08.08
申请人 ADVANTEST CORPORATION 发明人 TABATA MAKOTO;OKINO NOBORU
分类号 G01R31/28;G11C16/02;G11C16/34;G11C17/00;G11C29/12;G11C29/52;G11C29/56;(IPC1-7):G11C29/00 主分类号 G01R31/28
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