发明名称 |
Partially de-coupled core and periphery gate module process |
摘要 |
The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps. |
申请公布号 |
US6835662(B1) |
申请公布日期 |
2004.12.28 |
申请号 |
US20030619797 |
申请日期 |
2003.07.14 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
ERHARDT JEFF P.;KINOSHITA HIROYUKI;TABERY CYRUS |
分类号 |
H01L21/033;H01L21/3213;H01L21/8239;H01L21/8246;H01L27/115;(IPC1-7):H01L21/302;H01L21/476;H01L21/336 |
主分类号 |
H01L21/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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