INTEGRATED CIRCUIT PLANARIZING PROCESS

摘要

A planarizing process for producing a passivation or insulating layer immediately underlying an upper metallized layer on the surface of an integrated circuit having very large radius of curvature steps, thus providing a reliable base for the metallized layer. The process is comprised of the steps of depositing and defining first metal conductors on the surface of an integrated circuit, depositing a first dielectric layer over the surface of the integrated circuit including the conductors, the dielectric layer being comprised of material selected from the group comprised of silicon dioxide and silicon nitride, depositing and polymerizing a layer of negative isoprene resist over the surface of the dielectric layer, etching the surface of the isoprene and dielectric layers to a predetermined thickness over the metal conductors, cleaning the etched surface, and depositing a second dielectric layer over the surface selected from the group comprised of silicon dioxide and silicon nitride, whereby a surface having very large radius of curvature steps over the metal conductors is produced.